The disclosure relates generally to manufacturing processes for field effect transistors (FETs). More specifically, embodiments of the present disclosure include processing an integrated circuit for metal gate replacement.
In integrated circuit (IC) structures, a transistor is a critical component for implementing digital circuitry designs. Generally, a transistor includes three electrical terminals: a source, a drain, and a gate. By applying different voltages to the gate terminal, the flow of electric current between the source and the drain can be turned on and off. A common type of transistor is a metal oxide field effect transistor (MOSFET). One type of MOSFET is a “FinFET,” typically formed upon a semiconductor-on-insulator (SOI) layer and buried insulator layer. A FinFET can include a semiconductor structure etched into a “fin” shaped body, with one side of the fin acting as a source terminal and the other side of the fin acting as a drain terminal. A gate structure, which may include conductive materials such as metals, can be formed over one or more of the semiconductor fins. By applying a voltage to the gate structure, an electrically conductive channel can be created between the source and drain terminals of each fin in contact with the gate.
The gate of a transistor can be formed as a gate stack structure (i.e., a “metal gate stack”) composed of a metal separated from the semiconductor material of the fin by a gate dielectric layer. Two processing paradigms for fabricating a gate stack can include a gate-first approach or a gate-last approach. The gate-last approach can also be known as a “replacement metal gate” (RMG) process flow, in which other portions of the transistor (e.g., fin, source and drain contacts, channel region, etc.) are formed using a dummy gate that is replaced with the final gate after fabrication of other parts. Although RMG processes can offer a lower thermal budget (i.e., the amount of thermal energy transferred to a wafer during a temperature treatment) and higher levels of advantageous strain in a resulting finFET, RMG processes are typically complex and can require more restrictive design rules. Thus, the performance of a finFET formed through an RMG process is at least partially dependent on the methods of processing and forming the finFET.